This invention relates generally to transistor-transistor logic (TTL) circuits and more particularly, it relates to a TTL tri-level buffer which consumes less power in the tri-state mode than in the low logic state.
Typically, digital tri-level buffer circuits respond to an input signal either by coupling an output terminal to a supply voltage via an active pull-up device when the input signal is in a first logic state or be coupling the output terminal to a ground potential via a pull-down device when the input signal is in a second logic state. Further, tri-level buffer circuits are responsive to a tri-state control signal which disables both the active pull-up and pull-down devices when the control signal is active so as to provide a high impedance at the output terminal. However, such prior art buffer circuits have the disadvantage in that they consume the same amount of power when in the tri-state mode as when the output terminal is at the low logic state.
It would therefore be desirable to provide a TTL tri-level buffer which draws less current during the tri-state mode so as to reduce power consumption. This is achieved by utilizing three phase splitters instead of a single phase splitter in conventional designs so that a smaller amount of current will be drawn through the tri-state control line during the tri-state mode.